dg2523, dg2524 www.vishay.com vishay siliconix s16-2128-rev. a, 17-oct-16 1 document number: 67894 for technical questions, contact: analogswitchtechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 0.4 ? , low resistance and capacitance, dual dpdt / quad spdt analog switch description the dg2523 and dg2524 are four-channel single-pole double-throw (spdt) analog switches. the dg2523 has two control inputs that each controls a pair of single-pole double-throw (spdt). it is also known as a two-channel double-pole double-throw (dpdt) configuration. the dg2524 has an en pin to enable the device when the logic is low. the parts are designed to oper ate from 1.8 v to 5.5 v single power rail. all switches co nduct equally well in both directions, offering rail to rail signal witching and can be used both as multiplexers as well as de-multiplexers. the parts feature low control logic threshold. break-before-make switching is guaranteed. the dg2523 and dg2524 exhibit low parasitic capacitance, low leakage, and highly matched low and flat switch resistance over the full signal range characters that are important for precisi on analog designs. the high bandwidth and excellent total harmonic distortion (thd) performance make them ideal for both analog and digital signal switching in space constrain applications requiring high perfo rmance and efficient use of board space. the dg2523 and dg2524 come in pb-free qfn-16 package of 3 mm x 3 mm. benefits ? low and flat resistance ? excellent total harmonic distortion ? low parasiti c capacitance ? low voltage control interface features ? 1.8 v to 5.5 v single supply operation ? low resist ance: 0.4 ? / typ. at 2.7 v ? highly flat and matched r on ? low parasitic capacitance, c on = 26 pf, c off = 14.5 pf ? typical switch off leakage of 40 pa ? high bandwidth: 310 mhz ? guaranteed logic high 1.2 v, logic low 0.3 v ? break before make switching ? signal swing over v+ capable ? power down protection ? latch up current: 300 ma (jesd78) ?esd/hbm: > 6 kv ? material categorization: fo r definitions of compliance please see www.vishay.com/doc?99912 applications ? automatic test equipment ? data acquisition systems ? meters and instruments ? medical and healthcare systems ? communication systems ? audio and video signal routing ? battery powered systems ? computer peripherals ? data storage ? relay replacement functional block diagram and pin configuration in1, in2 no4 com2 no2 nc3 in3, in4 nc1 com4 1 2 3 12 11 10 49 56 8 16 15 14 13 nc2 gnd no3 com3 com1 no1 v+ nc4 top view dg2523dn qfn-16 (3 x 3) 7 in no4 com2 no2 nc3 en nc1 com4 1 2 3 12 11 10 49 56 8 16 15 14 13 nc2 gnd no3 com3 com1 no1 v+ nc4 top view dg2524dn qfn-16 (3 x 3) 7 control
dg2523, dg2524 www.vishay.com vishay siliconix s16-2128-rev. a, 17-oct-16 2 document number: 67894 for technical questions, contact: analogswitchtechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 notes a. signals on nc, no, or com, or in exceeding v+ will be clamped by internal diodes. limit forward diode current to maximum curr ent ratings. b. all leads welded or soldered to pc board. c. derate 17.3 mw/c above 70 c. d. manual soldering with iron is not recommended for leadless components. the miniqfn-16 is a leadless package. the end of the l ead terminal is exposed copper (not plated) as a result of the sing ulation process in manufacturing. a solder fillet at the exposed copper lip cannot be guaranteed and is not required to ensu re adequate bottom side solder interconnection. stresses beyond those listed under absolute maximum ratings ma y cause permanent damage to th e device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those in dicated in the operational sectio ns of the specifications is not implied. exposure to absolute maximum rating conditions for extended pe riods may affect device reliability. truth table dg2523 inx nc1, 2, 3, and 4 no1, 2, 3, and 4 0onoff 1offon truth table dg2524 en logic in nc1, 2, 3, and 4 no1, 2, 3, and 4 1x off off 0 0 on off 01 off on ordering information temperature rang e package part number min. order / pack. quantity -40 c to +85 c lead (pb)-free qfn-16 (3 mm x 3 mm) dg2523dn-t1-ge4 tape and reel, 2500 units DG2524DN-T1-GE4 absolute maximum ratings (t a = 25 c, unless otherwise noted) parameter symbol limit unit reference to gnd v+ -0.3 to +6 v in, com, nc, no a -0.3 to (v+ + 0.3) current (any terminal except no, nc, or com) 30 ma continuous current (no, nc, or com) 300 peak current (pulsed at 1 ms, 10 % duty cycle) 500 storage temperature (d suffix) -65 to +150 c package solder reflow conditions d qfn-16 250 power dissi pation (packages) b qfn-16 c 1385 mw
dg2523, dg2524 www.vishay.com vishay siliconix s16-2128-rev. a, 17-oct-16 3 document number: 67894 for technical questions, contact: analogswitchtechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 notes a. room = 25 c, full = as determined by the operating suffix. b. the algebraic convention whereby the most negative value is a mi nimum and the most positive a maxi mum, is used in this data s heet. c. typical values are for design aid only, not guaranteed nor subject to production testing. d. guarantee by design, not su bjected to production test. e. v in = input voltage to pe rform proper function. f. crosstalk measured between channels. specifications (v+ = 3 v) parameter symbol test conditions unless otherwise specified v+ = 3 v, 10 %, v in = 0.5 v or 1.4 v e temp. a limits -40 c to +85 c unit min. b typ. c max. b analog switch analog signal range d v no , v nc , v com full 0 - v+ v on-resistance r on v+ = 2.7 v, v com = 0 to 2.7 v, i no , i nc = 100 ma room - 0.40 0.55 ? full - - 0.65 r on flatness d r on flatness v+ = 2.7 v, v com = 0 to v+, i no , i nc = 100 ma full - 0.03 0.08 r on match d ? r on room - 0.05 - switch off leakage current i no(off) , i nc(off) v+ = 5.5 v, v no , v nc = 0.5 v / 4 v, v com = 4 v / 0.5 v room -1 0.04 1 na full -5 - 5 i com(off) room -1 0.17 1 full -5 - 5 channel-on leakage current i com(on) v+ = 5.5 v, v no , v nc = v com = 0.5 v / 4 v room -1 0.17 1 full -5 - 5 digital control input high voltage v inh full 1.2 - - v input low voltage v inl --0.3 input capacitance c in full - 5 - pf input current i inl or i inh v in = 0 or v+ full -1 - 1 a dynamic characteristics turn-on time t on v no or v nc = 1.5 v, r l = 50 ? , c l = 35 pf room - 38 60 s full - - 70 turn-off time t off room - 0.43 1 full - - 3 break-before-make time t d full 1 - - charge injection d q inj c l = 1 nf, v gen = 1.5 v, r gen = 0 ? room - -19 - pc -3 db bandwidth bw r l = 50 ? , c l = 5 pf room - 310 - mhz off-isolation d oirr r l = 50 ? , c l = 5 pf, f = 100 khz room --82- db r l = 50 ? , c l = 5 pf, f = 1 mhz - -55 - crosstalk d, f x talk r l = 50 ? , c l = 5 pf, f = 100 khz - -89 - r l = 50 ? , c l = 5 pf, f = 1 mhz - -61 - total harmonic distortion plus noise thd + n 2.5 v, signal peak to peak voltage r l = 32 ? , f = 1 khz - -100 - no, nc off capacitance d c no(off) f = 1 mhz room - 14.5 - pf c nc(off) - 14.5 - channel-on capacitance d c no(on) -26- c nc(on) -26- power supply power supply range v+ 1.8 - 5.5 v power supply current i+ v in = 0 or v+ full - 29 60 a
dg2523, dg2524 www.vishay.com vishay siliconix s16-2128-rev. a, 17-oct-16 4 document number: 67894 for technical questions, contact: analogswitchtechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 typical characteristics (t a = 25 c, unless otherwise noted) r on vs. v com and supply voltage supply current vs. input voltage supply current vs. supply voltage r on vs. analog voltage and temperature supply current vs. temperature leakage current vs. temperature 0.34 0.36 0.38 0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 r on -on-re s i s tance ( ) v com - analog voltage (v) v+ = +1.8 v v+ = +3.0 v v+ = +2.3 v v+ = +5.0 v t a = 25 c i s = 100 ma v+ = +3.6 v 10 100 1000 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 i+ - s upply current (a) v in - input voltage (v) v+ = 5 v t = 25 o c v+ = 3 v v+ = 1.8 v 10 20 30 40 50 60 70 80 90 100 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 i+ - s upply current (a) v+ - s upply voltage (v) t a = 25 c v in = 0 v 0.24 0.26 0.28 0.30 0.32 0.34 0.36 0.38 0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.0 0.5 1.0 1.5 2.0 2.5 3.0 r on -on-re s i s tance ( ) v com - analog voltage (v) +85 c +25 c -40 c v+ = +3.0 v i s = 100 ma 0 5 10 15 20 25 30 35 40 45 50 55 60 -40-200 20406080100 i+ - s upply current (na) temperature ( c) v+ = +3 v in = 0 v -200 0 200 400 600 800 1000 1200 1400 -40-200 20406080100 leakage (pa) temperature ( o c) v+ = 3.3 v v com = 0.5 v v no/nc = 2.8 v i no/nc(off) i com(off) i com(on)
dg2523, dg2524 www.vishay.com vishay siliconix s16-2128-rev. a, 17-oct-16 5 document number: 67894 for technical questions, contact: analogswitchtechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 typical characteristics (t a = 25 c, unless otherwise noted) leakage current vs. drain voltage insertion loss, off-isolatio n crosstalk vs. frequency switching time vs. temperature switching threshold vs. supply voltage -100 -80 -60 -40 -20 0 20 40 60 80 100 00.511.522.533.5 leakage current (pa) v com - drain voltage (v), v no/nc = -v com v+ = 3.3 v i com(on) i com(off) i no/nc(off) -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 100k 1m 10m 100m 1 g lo ss , oirr, x talk (db) fre q uency (hz) lo ss oirr x talk v+ = +3 v r l = 50 s witching s peed ( s ) temperature ( c) t off , v+ = 5.5 v t off , v+ = 3 v t off , v+ = 1.8 v t on , v+ = 5.5 v t on , v+ = 3 v t on , v+ = 1.8 v 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85 0.90 1.522.533.544.555.5 v th - s witching thre s hold (v) v+ - s upply voltage (v) v ih v il
dg2523, dg2524 www.vishay.com vishay siliconix s16-2128-rev. a, 17-oct-16 6 document number: 67894 for technical questions, contact: analogswitchtechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 typical characteristics (t a = 25 c, unless otherwise noted) charge injection vs. analog voltage switching time vs. supply voltage capacitance vs. analog voltage -40.0 -35.0 -30.0 -25.0 -20.0 -15.0 -10.0 -5.0 0 00.511.522.53 q inj - charge injection (pc) v no/nc - analog voltage (v) v+ = 3 v 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 1.5 2 2.5 3 3.5 4 4.5 5 5.5 s witching s peed ( s ) v+ - s upply voltage (v) t = 25 c v analog = 1/2 v+ t on t off 0 5 10 15 20 25 30 35 40 0.0 0.5 1.0 1.5 2.0 2.5 3.0 capacitance (pf) analog voltage (v) v+ = 3 v c com(on) c no/nc(off)
dg2523, dg2524 www.vishay.com vishay siliconix s16-2128-rev. a, 17-oct-16 7 document number: 67894 for technical questions, contact: analogswitchtechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 test circuits fig. 1 - switching time fig. 2 - break-before-make interval fig. 3 - charge injection switch input c l (includes fixture and stray capacitance) v+ in no or nc c l 35 pf com logic input r l 50 v out gnd v+ 50 % 0 v logic input switch output t on t off logic ?1? = switch on logic input waveforms inverted for switches that have the opposite logic sense. 0 v switch output v out v com r l r l r on 0.9 x v out t r 5 ns t f 5 ns v inh v inl = + < < ( ) c l (includes fixture and stray capacitance) nc v no no v nc 0 v logic input switch output v o v nc = v no t r < 5 ns t f < 5 ns 90 % t d t d in com v+ gnd v+ c l 35 pf v o r l 50 v inl v inh off on on in v out v out q = v out x c l c l = 1 nf r gen v out com v in = 0 - v+ in gnd v+ v+ in depends on switch configuration: input polarity determined b y sense of switch. + nc or no v gen
dg2523, dg2524 www.vishay.com vishay siliconix s16-2128-rev. a, 17-oct-16 8 document number: 67894 for technical questions, contact: analogswitchtechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 fig. 4 - off-isolation fig. 5 - channel off / on capacitance vishay siliconix maintains worldw ide manufacturing ca pability. products may be manufactured at one of several qualified locatio ns. reliability da ta for silicon technology and package reliability represent a composite of all qu alified locations. for related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?67894 . in gnd nc or no 0 v, 2.4 v 10 nf com off isolation 20 log v com v no / nc r l analyzer v+ v+ com = nc or no f = 1 mhz in com gnd 0 v, 2.4 v meter hp4192a impedance analyzer or equivalent 10 nf v+ v+
package information www.vishay.com vishay siliconix revision: 09-may-16 1 document number: 72208 this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 qfn-16 lead (3 x 3) notes (1) all dimensions are in millimeters. (2) n is the total num ber of terminals. (3) dimension b applies to metallized terminal and is me asured between 0.25 and 0. 30 mm from terminal tip. (4) coplanarity applies to the exposed heat sink slug as well as the terminal. (5) the pin #1 identifier may be either a mold or marked feature, it must be located within the zone indicated. dim. variation 1 variation 2 millimeters inches m illimeters inches min. nom max. min. nom max. min. nom max. min. nom max. a 0.80 0.90 1.00 0.031 0.035 0.039 0.80 0.90 1.00 0.031 0.035 0.039 b 0.18 0.23 0.30 0.007 0.009 0.012 0.18 0.25 0.30 0.007 0.010 0.012 d 2.90 3.00 3.10 0.114 0.118 0.122 2.90 3.00 3.10 0.114 0.118 0.122 d2 1.00 1.15 1.25 0.039 0.045 0.049 1.50 1.70 1.80 0.059 0.067 0.071 e 2.90 3.00 3.10 0.114 0.118 0.122 2.90 3.00 3.10 0.114 0.118 0.122 e2 1.00 1.15 1.25 0.039 0.045 0.049 1.50 1.70 1.80 0.059 0.067 0.071 e 0.50 bsc 0.020 bsc 0.50 bsc 0.020 bsc l 0.30 0.40 0.50 0.012 0.016 0.020 0.30 0.40 0.50 0.012 0.016 0.020 ecn: t16-0233-rev. d, 09-may-16 dwg: 5899 -c- c 0.08 c 0.10 // -a- -b- e s eatin g plane a3 a1 a nx side view (3) terminal tip expo s ed pad d d/2 e/2 bottom view top view c 0.25 c 0.25 e2/2 e2 d2 d2/2 l e 3 x e 3 x e c 0.10 m a b 4xb (3) (4) (4)
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